Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today’s FPGA designers advanced capabilities in a productive work environment.
General Defects Repaired in 10.7
* dvt94966 – The capstat command and options have been redesigned. The capstat option for vsim is as follows:
-capstats[=[,]] Enables capstats report
are du, decl, line, eor and filename=.
Arguments are specified separated by comma.
The argument du has suboptions: summary, details and duname=
These suboptions can be specified separated by ‘+’
The capstat comamnd is as follows:
capstats [-du [+summary | +details] [+duname=]] [-decl] [-line] [-filename ]
If no option is specified, capstats prints summary report under top categories.
A design unit based breakup of memory can be seen by specifying -du option. For extra details, summary or details options can be used. Specific design units can be specified using duname suboption. If design units are specified, then design unit based report is generated only for the specified design units.
-decl option prints declaration based report for dynamic objects.
-line option prints line based report for dynamic objects.
* dvt97602 – (results) If the file specified with vsim’s "-f" switch was a DOS format file containing line-continuation character(s) ‘', then vsim emitted incorrect "(vsim-3369) Top-level design unit specified more than once" errors. The error message didn’t contain a module name, but just an empty ” containing a new-line character.
User Interface Defects Repaired in 10.7
* dvt70665 – Questa & ModelSim fail to run if installed in a path containing spaces. This issue is now resolved.
* dvt102099 – The noforce command incorrectly returns an error status when used in vsim -batch mode. This issue has been resolved.
* dvt104114 – An incorrect warning "VSIM-3581" is no longer issues when using -appendlog along with -restore or -load_elab options.
* dvt36562 – Using the mouse scroll wheel in the Memory View window now scrolls the window contents correctly.
SystemVerilog Defects Repaired in 10.7
* dvt96999 – (results) Optimized full timing gate-level cells could drive incorrect values where 2 wired bufif0/bufif1/notif0/notif1 primitives with shared selects (select having an X or Z value) drive a single output port.
* dvt97601 – (results) vsim crashed, when multiple specify paths or multiple timing checks were present on the same line (in specify block), and "-sdfreport" was specified on vsim command line.
* dvt97533 – (results) Interconnect delay was not correct for all to X transitions as per 1364-2001 LRM.
* dvt96725 – (results) A protected object cannot have its value reported using VPI.
* dvt99392 – (results) Unnamed generate block in a protected region would not have its name changed to when it was involved in the output from a %m format specifier. This has been fixed.
* dvt99463 – Fixed memory leak when forces on optimized cell ports are present.
* dvt32206 – (results) $nochange timing check did not work properly in all cases.
* dvt88864 – (results) Fixs were made to SV extension -svext=iddp. For existing usage of vlog/vopt -svext=iddp, a recompilation from SV files is required due to this change.
* [nodvtid] – Questa now supports "integral_number"s as a part of an "enum_identifier" within an "enum_name_declaration" production.
* [nodvtid] – In fatal errors involving virtual interfaces Questa may have emitted an incorrect file number in the message.
* dvt102853 – Fixed a simulator internal error when a DPI open array with an unsized packed dimension is used. The message is similar to: Questa has encountered an unexpected internal error: ../../src/vsim/svdpi_runtime.c(2216).
VHDL Defects Repaired in 10.7
* dvt93451 – (results) Vsim crashed when bit slices wider than 256, of VHDL signals, were read through built-in UVM backdoor functions.
* dvt94049 – The compiler incorrectly reported the following error when encountering an alias of an operator function instance:
** Error: Alias with operator symbol designator must denote a function.
The compiler also incorrectly generated code for newly-defined operator functions with generic-typed parameters.
* dvt94831 – Added expected return type to the error message reporting overload resolution of a function call failed.
* dvt93277 – The vmake command would not work when there was a dependency on an encrypted design unit.
* dvt96070 – An error could occur if elaboration of a VHDL required a function call. To have an error the function would need to have a case statement where one or more of the case statement’s choices are ranges.
* dvt95670 – The attributes A’range and A’reverse_range would give incorrect ranges if A’s bounds are defined with impure function calls.
* dvt97035 – (results) In some cases, assignment statement within a for loop would have their line number changed to something else. This would result in incorrect coverage information being generated. Stepping through the loop would case the source display to jump to an incorrect line.
* dvt98225 – (results) In certain conditions involving a VHDL package, vopt issued an incorrect "(vopt-3369) Top-level design unit specified more than once." error. This has been fixed.
* dvt97593 – Direct instantiation of an entity with a package instantiation in one of the generic map associations could cause incorrect code to be generated by the compiler, possibly leading to a loading failure message from the simulator.
* dvt98805 – (source) In case, case generate, selected signal assignments, and selected variable assignments statements an error was not reported if the selector expression was a range. For example "CASE s’RANGE" would not result in an syntax error. It was either treated as length of the range or an internal error was reported from vcom or vopt.
* dvt99166 – Writing a STRING to the FILE STD.TEXTIO.OUTPUT (which is stdout) using the function STD.TEXTIO.WRITE[TEXT,STRING] could result in a crash if the string contained two terminating LF (0x0a) characters.
* dvt99443 – Record aggregate with OTHERS could result in a vcom or vopt crash if the expression was not of the same subtype as the record element(s) being associated.
* dvt101580 – Certain styles of continuous selected signal assignment statements with zero delay would not execute properly when optimized, either in an optimized design or a design compiled with the PE version of the product.
* dvt103341 – (source) If the a bound of a range contained a function call, in some cases vcom failed to check to see if an actual argument to a function was in the subtype of the formal argument. This would occur if the actual argument was locally static and the formal’s subtype was locally static. This would allow invalid code to execute. Depending how the function handle invalid argument values the simulation could generate errors or incorrect results.
* dvt103675 – In some cases where are large number of objects are declared the order of declaration could negatively impact vcom performance.
* dvt104516 – (results) Predefined attribute S’LAST_VALUE could produce incorrect results if it was evaluated on a changing composite signal as deltas were occurring during the same timestep.
* dvt103546 – The implicit matching operators for STD_ULOGIC, when the operands were locally static, would not be evaluated correctly by the compiler when performing an optimization to replace the expression with a known value
* dvt103968 – Subprogram instantiation called with out-of-range actual would sometimes not be caught as an error.
* dvt103025 – (results) In some specific cases of procedures being used before they are defined the tool was giving incorrect output. This has been fixed.
* dvt67231 – Special characters in a comment that was inside an encrypted region could cause a parsing error.
SystemC Defects Repaired in 10.7
* dvt92791 – Bug in the sccom distributed flow with missing systemc exported modules has been fixed.
* dvt95642 – sccom merge error (sccom-6165) with a circular dependent forward declared module instantiation has been fixed.
* dvt81733 – (results) vsim option ‘-scchkpntrestore’ will allow checkpoint/restore feature with SystemC in the design as long as the SystemC hierarchy is dummy wrapper without any active constructs like signals, variables, processes etc. If the design has active SystemC usage, vsim will try to ignore the unsupported constructs and proceed with the simulation, but if there is a usage that cannot be ignored, vsim will throw a fatal run time error. SystemC designs compiled with the 10.6 release will need to be recompiled with the 10.6a release.
* dvt99466 – While trying to print the vsim-6577 error, for a sc_module, sc_port or a sc_prim_channel global or static SystemC object that is being destroyed at exit time, vsim might crash in some odd scenarios. This issue is now fixed. vsim will report a vsim-6522 warning instead and exit gracefully.
Mixed Language Defects Repaired in 10.7
* dvt95057 – (source) Fixed a bug where a SystemVerilog task was being allowed inside a SystemVerilog function even if it contained a DPI task call. The DPI task call can potentially have delays in it. It is illegal to call a task from a function in SystemVerilog but we do allow it in case task does not contain any delays. Now, the check for the delay in the task also includes the check for DPI task call. This change may result in some of the customer designs failing to compile. It is recommended to fix the designs.
* dvt96160 – (results) Now built-in version of uvm_hdl_read, correctly reads the values from arbitrary slices of VHDL array signals with non-zero LSB/MSB indices.
WLF and VCD logging Defects Repaired in 10.7
* dvt93896 – The [wlfman filter] and [wlf2vcd] performance has been dramatically improved for WLF files containing large numbers of single bit Verilog nets.
General Enhancements in 10.7
* dvt15443 – When vsim crashes with SIGSEGV signal, we were only giving HDL call stack. But, it wasn’t complete stack in case of the crash in user’s C code (like DPI/PLI etc). Now, vsim will generate stacktrace file and print full stacktrace in transcript as well, in addition to existing HDL call stack.
* dvt94809 – Added switch "-pdupath[=<lib_path>]" which can be used with vsim to specify library path for PDU when library is moved after top level optimized design unit creation. If optional <lib_path> is not specified PDU will be looked into current working directory.
* [nodvtid] – (results) -novopt flow has been deprecated and commands will flag below error now.
** Error (suppressible): (vlog-12110) All optimizations are disabled because the -novopt option is in effect.
This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for
Debug or PLI features, please see the User’s Manual section on Preserving Object Visibility with vopt. -novopt
option is now deprecated and will be removed in future releases.
Using -novopt with optimized design in vsim will also flag below error.
** Error (suppressible): (vsim-12110) -novopt option has no effect when used with the optimized design.
-novopt option is now deprecated and will be removed in future releases.
In 10.7 release, user can suppress this error. But, it is recommended to remove any dependency on -novopt flow from user’s design environment. Future releases will remove -novopt flow completely.
User Interface Enhancements in 10.7
* dvt97716 – (results) Systemverilog Named Events now display a value in the GUI when examined or shown in any window where named items display values. The value for a Named Event will be the last simulation time the event was triggered. It will be displayed in the form "->@45 ns". If the event was never triggered, then the value "" will be displayed.
SystemVerilog Enhancements in 10.7
* [nodvtid] – Use the vlog switch svext=+mttd to reinterpret “" (tick-tick-double quote) as `" (tick-double quote) within macro text expansion.
* [nodvtid] – Vlog can optionally ignore commas, ",", and right parens, ")", when found within a `" `" string that forms a list of macro argument actuals within another macro expansion. The -svext=+mtdl switch enables this behavior.
* dvt96810 – (results) The new default vlog/vopt behavior to ignore PATHPULSE$ specparam’s can be overriden by using the +pathpulse command line option.
* [nodvtid] – Parenthesis around a specify terminal descriptor are now recognized as an LRM extension. The SV parser will now accept parens when the error message 13290 is either suppressed or demoted to a warning.
* [nodvtid] – Allow empty procedural case statements. I.e.: case statements with no branches defined. By default the vlog compiler will continue to emit an error when no branches are defined. This error is suppressible.
* [nodvtid] – Vlog’s command line option -svfilesuffix now accepts more characters as valid.
* dvt103176 –
Constraint solver vsim switch -solvefailseverity has been enhanced. The error message for randomize() failure and randomize(null) failure can be controlled separately with different severities. The existing usage of -solvefailseverity is not impacted.
Specify error message severity when randomize() and randomize(null) failures are detected.
When both and are present, specifies the severity of randomize(),
and specifies the severity for randomize(null). When only is present, the
severity setting applies to both randomize() and randomize(null).
Valid values for both and :
0 – no error
1 – warning
2 – error
3 – failure
4 – fatal
The companion modelsim.ini variable has been enhanced for the similar change.
* dvt5888 – Questa now supports reading vector based port declarations in evcd file. The option to read this file is -vcdstim which is an existing option. There is no additional option needed to use this functionality. Vector based evcd file can be generated from Questa using +dumpports+collapse option.
SystemC Enhancements in 10.7
* [nodvtid] – sccom has a new option ‘-sctop ‘. This option should be used along with the ‘-nodebug’ option. Every SystemC module specified with the SC_EXPORT_MODULE() macro should be specified on the sccom command line with the ‘-sctop ‘ option during compilation, e.g: sccom -sctop -sctop … .
WLF and VCD logging Enhancements in 10.7
* dvt94883 – In post-sim mode (vsim -view), The ‘Cover Directives’ window is now populated.
About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused.
In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.
The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
About Mentor Graphics. Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Product: Mentor Graphics ModelSim
Version: SE 10.7
Supported Architectures: x64
Website Home Page :
System Requirements: PC
Supported Operating Systems: Windows 7even or newer
Size: 755.6 mb